1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a semiconductor memory device used for multi-level flash memories, multi-level EEPROMs and multi-level EPROMs.
The MOSFET structure made in such a manner that a floating gate (charge storage layer) and a control gate are provided on a semiconductor substrate, is well known as one of the memory cells in a flash memory.
Ordinarily, in one memory cell of a flash memory, one-bit data, that is, data “0” or “1” is stored. Further, whether the data in a memory cell is “0” or “1” can be identified through the amount of charges stored in the floating gate.
On the other hand, in order to secure a large data capacity, recently the development of a multi-level memory system according to which multi-bit data are stored in one memory cell is being pushed forward. For instance, in the case of the four-level memory system, “0”, “1”, “2” or “3” is stored in one memory.
In a multi-level flash memory, “which data is stored in a memory cell” is judged depending on the amount of charges stored in the floating gate.
The stored state of data, that is, the relationship between the data and the amount of charges in the floating gate will now be described by taking a four-level flash memory for example.
The data “0” corresponds to an erased state.
The erased state is a state in which positive charges are stored in the floating gate. That is, in the erased state, the floating gate is charged positively with reference to the neutral state in which the amount of charges in the floating gate is zero.
The erased state is obtained in such a manner that, for instance, a high voltage (about 20V) is applied to the semiconductor substrate, the control gate is set to the ground voltage (0V), and the positive charges are moved from the semiconductor substrate to the floating gate.
The data “1”, “2” and “3” correspond to programmed states.
The programmed state is a state in which negative charges are stored in the floating gate. However, the amount of negative charges in the floating gate which is in the data “2” state is set so as to be larger than the amount of negative charges in the floating gate in the data “1” state; the amount of charges in the floating gate in the data “3” state is set so as to be larger than the amount of negative charges in the floating gate in the data “2” state.
In the programmed state, the floating gate is charged negatively with reference to the neutral state in which the amount of charges in the floating gate is zero.
The programmed state is obtained in such a manner that, for instance, the semiconductor substrate, the source and the drain are set to the ground voltage, respectively, a high voltage (about 16V) is applied to the control gate, and the negative charges are moved from the semiconductor substrate to the floating gate.
During a programming operation, in a cell in which the data “0” is desired to be maintained, the source, the drain and the channel are set to 5V, respectively. In this case, even if the high voltage (about 16V) is applied to the control gate, and the substrate is set to the ground voltage (0V), the data “0” is maintained since the positive charges are held in the floating gate.
In this way, by one memory cell, four kinds of programmed states (“0”, “1”, “2” and “3”) can be realized.
As for flash memories, those flash memories which have NAND memory cell units are known.
Each of these memory cell units has a memory cell column consisting of a plurality of (for example, four) memory cells, a first select transistor connected between one end of the memory cell column and a bitline, and a second select transistor connected between the other end of the memory cell column and a source line.
In this connection, it is noted that the source line is used in common for all the memory cell units.
In the case of a flash memory with NAND memory cell units, at the time of programming of data “0”, the bitline is set to the power supply voltage (for example, 3V), the gate of the first select transistor is set to the power supply voltage VCC, the control gate of the selected memory cell is set to a first high voltage (for example, 16V), and the voltage at the control gates of the unselected memory cells is set to a second high voltage (for example, 10V), whereby the charges stored in the floating gate of the selected memory cell is retained.
In this case, the channels of the respective memory cells in the NAND memory cell unit are connected to the bitline via the first select transistor, so that the voltage at each memory cell assumes, to take into consideration the so-called threshold voltage drop of the first select transistor, a predetermined voltage below the power supply voltage VCC (for example, 3V) at the beginning.
After this, when the first select transistor becomes non-conductive, the channel voltage of the respective memory cells in the NAND memory cell unit rises through the electrostatic capacitance produced between the control gates and the channels. For instance, if the coupling ratio of the electrostatic capacitance is 50%, then the channel voltage becomes about 5V.
However, when negative charges are accumulated in the floating gates of the respective memory cells, the threshold voltage of the memory cells becomes high. As a result, the channel voltage of the respective memory cells in which the data “0” is being programmed fall in inverse proportion as the threshold voltage of the memory cells increases, and the reliability in respect of the retention of the date “0” falls.
For example, in case the threshold voltage of the memory cells is −1V, when the voltage of the control gates is about 0V, the channel voltage becomes about 1V, and, when the voltage of the control gates is about 10V, the channel voltage becomes about 6V (Coupling ratio: 50%).
Further, in case the threshold voltage of the memory cells is 3V, when the voltage of the control gates is about 1V, the voltage of the channels becomes about 0V, and when the voltage of the control gate is about 10V, the channel voltage becomes about 4.5V (Coupling ration: 50%).
In the case of a flash memory with NAND memory cell units, the data in the respective memory cell can be read out in such a manner that a predetermined read voltage is applied to the control gate, so that, in accordance with the data of the memory cell, the particular memory cell is brought into ON or OFF state, and the current flowing through the channel of the memory cell at this time is detected.
Here, by preparing three kinds of read voltages, four kinds of programmed states (the kinds and amounts of the charges in the floating gate, that is, the states in which the threshold voltages differ from one another) can be identified.
Further, the NAND memory cell units are each constituted in such a manner that a plurality of memory cells are connected in series and, thus, characterized in that the cell current when a read operation is performed is small in amount (for example, about 1 μm).
As for the read time, it is pointed out that, if the bitline capacitance coupled to the selected memory cell is about 5 pF for instance, then a time of about 5 μs is required for the bitline voltage to be varied by 1V by the cell current.
In order to read out the data of the memory cells at high speed by the use of a small amount of current, for instance an N-channel MOS transistor is connected between the respective bitline and the read circuit, so that a voltage of about 2V is applied to the gate of said MOS transistor to precharge the bitline.
In this case, if it is assumed that the threshold voltage of the N-channel MOS transistor is about 1V, then the bitline is precharged to about 1V by taking into consideration the so-called threshold voltage drop of said MOS transistor.
When the bitline is precharged, the N-channel MOS transistor becomes gradually higher in resistance until it becomes non-conductive. However, the precharge of the bitline is not continued until the N-channel MOS transistor becomes completely non-conductive if the substantial precharge time is taken into consideration.
During a read operation, a cell current flows to the selected memory cell, and, when the voltage at the bitline falls, the channel resistance of the N-channel MOS transistor connected to the bitline is lowered in resistance, so that it becomes possible to sense the voltage variation (the data of the memory cell) of the bitline at high speed by detecting this state.
The variation in the channel resistance of the N-channel MOS transistor can be detected by comparing the resistance value of the channel resistance of said MOS transistor with the resistance value of a so-called reference resistor. Due to this, current paths are provided to the reference resistor, the N-channel MOS transistor and the memory cells.
However, in case, by such a read operation, the data of a plurality of selected memory cells are read out at the same time, it happens that, in response to the threshold voltages of the respective selected memory cells, a large current flows through the source line serving in common for all the cell units, or conversely, no current at all flows to said source line.
For instance, in case cell currents flow to almost all the selected memory cells, that is, in case the data in almost all the selected memory cells are “0”, a large current flows to the source line, so that the voltage in the source line varies. The voltage variation in the source line increases the state in which the data in the selected memory cells cannot be accurately read out.
As described above, if the threshold voltages of the memory cells in a memory cell unit is high, then the channel voltages of the memory cells do not rise sufficiently, and therefore, there is the fear that, in the selected memory cell, not the data “0” but the data “1” may be programmed.
Further, at the time of reading, it takes much time to detect the state of a memory cell to which a small amount of cell current flows, but, if the state of the memory cell is to be detected at high speed, an accurate detection of the cell state cannot be carried out.